Low power is the holy grail for the next few decades in semiconductor industry. And while we have abstractions to manage complexity of design via EDA tools - it is not abstract enough. I am planning to write an article about this and I would love to bounce off ideas for orchestrating this new kind of complexity that will show (and already is showing) at the device level (teaser: integration of RRAM, MRAM etc.). How would you approach this?
@amitabh
Amitabh Yadav
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Based at École Polytechnique Fédérale de Lausanne (EPFL) where I develop implantable neural interface ASICs with on-chip signal processing and machine learning.
https://amitabh.chPosts
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